At DAC, Cadence announced a full suite of tools that they have been working on with TSMC to create what they are calling the CoWoS Design Ecosystem. I met with John Murphy and Samta Bansal to find out more. The first obvious question is CoWoS, what is that? It stands for chip-on-wafer-on-substrate (or sometimes on-silicon) and is TSMC’s name for their heterogeneous silicon interposer approach. Heterogeneous in the sense that all the die on the interposer do not need to be from the same semiconductor process.
As a test vehicle the designed and manufactured the first heterogeneous CoWoS module. There were 3 die: a 40nm memory, a 65nm GPS and a 28nm SoC, all put together on a 65nm silicon wafer. And it is yielding. Nobody is saying how much yet, but just as with the Xilinx part, one of the major reasons for doing this sort of design is to get the learning experience of what it takes to make an economic solution.