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Etron designing DRAMs for through silicon vias

Posted on June 3, 2012 by John in News - No Comments

TAIPEI – Etron Technoogy Inc. has started work on buffered DRAM designs geared for 3-D ICs using through-hole vias. The company is also working on an upgrade of a low-cost gesture recognition module.

Chip stacking technology has the potential to disrupt business models and traditional systems design, said Nicky Lu, the company’s founder and chief executive.

Both more and less dense memory parts will be needed to support a variety of different kinds of 3-D chip stacks for different applications, said Lu known for his work driving Taiwan’s submicron program.  “Most leading companies now claim TSVs will start in 2014, but I think 2015 is the first year of their real impact,” said Lu.

In the short term, the stacks will disrupt traditional thinking about the memory hierarchy in systems design. Long term, the stacks will include not only logic and memory die but optical, power. MEMS and bio components as well, he said.

Full article at EETimes: Etron designing DRAMs for through silicon vias.

3D, IC, memory, stack, TSV

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