Increases in wafer sizes have been a natural evolution and manufacturing efficiency improvement for the semiconductor industry for decades. However, this next transition, the costs entailed, and the state of the industry might make this transition a little different, particularly for defense. What are the issues and what’s at stake?
Integrated circuits…semiconductors…chips. The meanings are generally synonymous. A semiconductor device, regardless of whether it is an individual transistor, a microprocessor, flash or RAM memory, or any of other various devices, generally are made on large, circular wafers made of silicon (though there are exceptions). As the technology has progressed over the decades, gains in performance have been brought by these primary “levers”: reduction in transistor size, larger wafer sizes, increased clock frequency, and ingenious design architectures. Some of these have already played-out, while some are soon reaching the limit of where the cost for improvement is less than the return. The focus of this discussion is manufacturing cost, specifically where primarily transistor and wafer size are key drivers.
By reducing the size of the individual transistors, more and more functionality has been packed onto each chip. Early computers started with “vacuum tube” circuits, progressing to individually wired transistors, to the use of integrated circuits, which led to the microprocessor. An early microprocessor, the MOS6502 used in the original Apple II computer, had a mere 3500 transistors, each 16 micrometers in size, whereas a new AMD Tahiti graphics processor has over 4 billion transistors, each 28 nanometers in size.
For various reasons, including improved manufacturing efficiency, increased die size (less die packed onto each wafer), reduction in capital equipment expenditure, and factory cost optimization, there has been a steady increase in silicon wafer size. Though very early wafers were quite small (1 inch), standardized wafers moved from 100mm (4 inch) in size in the mid-1970’s though 300mm (12 inch) in the early 2000’s. Each size increase generally doubled the number of die manufactured on each wafer. Though some process equipment is limited in the amount of area processed in a given time due to physics, for other equipment the increased wafer size means that many more die are processed each hour. Along with the wafer size increase comes the opportunity to redesign the factory. For example, during the 200mm to 300mm wafer size transition that started in the late 1990′s, automated material handling was standardized which included use of minienvironment carriers for the wafers. These improvements helped efficiency and reduced the cost of clean room space for the fab. The high cost of each wafer transition has generally curtailed any new technology (i.e. transistor size) improvements on the previous wafer size.
However, these manufacturing improvements have come at a high price. The cost of a new semiconductor fab can run on the order of $US 5B or more, which has created an environment only relatively few players can afford. Consolidation has hit the industry hard, and many familiar names in the business have either gone to a fabless model where their designs stay in-house and manufacturing is outsourced, or have closed up shop entirely.
The next wafer size transition, to 450mm (18 inch) wafers, has been in the works for some time. While proponents claim that a wafer size increase is needed every ten years, the projected date of 2018 for 450mm high volume manufacturing is far past the original target date of 2012. Assuming the issues of who pays for the research and development (chipmakers or suppliers or some combination) is worked out and things progress, and what efficiencies are truly gained, the estimated cost of a new 450mm fab manufacturing 11nm transistors is on the order of $US 10B, putting the cost out of reach to all but a select few manufacturers.
So, what really is the implication for security? The companies who will likely be able to afford a 450mm fab include Intel, Samsung, Taiwan Semiconductor Manufacturing Company (TSMC), and perhaps, GLOBALFOUNDRIES. TSMC and GLOBALFOUNDRIES are foundries—hired guns who manufacture chips for companies who have given up their own fabs and others who have focused on only designs from their genesis. A significant portion of the specialty chips used in all consumer products are manufactured at foundries. TSMC, being primarily located in Taiwan, owns a majority of the foundry market. Another large player, GLOBALFOUNDRIES, a spin-off of AMD with fabs in Germany, New York, and Singapore, is now completely owned by Advance Technology Investment Company in Abu Dhabi.
Up until last year, it was assumed that GLOBALFOUNDRIES’ next major fab would be built in Dubai. This may still be the case. If so, the fab will likely run 450mm wafers, as the leading-edge technology will only be available on this platform after the wafer transition. This would move all leading edge, specialty semiconductor manufacturing away from the US to overseas. Manufacturers that have not built a 450mm fab will be left out in the cold when looking to upgrade to the latest transistor size. This explains why, given the current conditions, Homeland Security’s IARPA program, called the Trusted Integrated Circuit program, assumes that leading edge, front-end processing (creating the transistors) for specialized, secure integrated circuits will be performed outside the US.
Is there anything that could change the equation? Fortunately, yes there is.
Last November, the State of New York College of Nanoscale Science and Engineering (CNSE) announced a two phase, New York State centered consortium that is focused on R&D and prototyping for 22nm and 14nm nanochip architectures and R&D for an eventual transition to a 450mm wafer size. The first phase funding is $US 4.4B from the Consortium Partners and $US 400M of State capital support. The second phase of this program, if agreed upon, provides an additional combined investment of approximately $US 3.3B and the creation of a significant number of jobs. The agreement will contain provisions that if any Consortium member determines, directly or indirectly, to build a 450mm plant anywhere in the world that at least one such 450mm facility would be built at an appropriate site in New York State.
It appears that a 450mm wafer transition is moving forward. Ultimately, it would behoove Homeland Security and DARPA to find a secure solution to specialized, leading edge semiconductor manufacturing that is outside of the commercial sector. However, until that solution is found, hopefully the State of New York will be successful in retaining multiple 450mm fabs from the Consortium Partners. In parallel, pursuing alternative paths, such as a mini-foundry or microfab, would be judicious. Those paths will be addressed in future commentaries.